A pseudo-SRAM has been known, which has a basic element of DRAM and is configured to be so operated as SRAM. The pseudo-SRAM is non-synchronous in view of the specification, which is similar to the conventional SRAM. The pseudo-SRAM is configured to have a basic element of DRAM. The pseudo-SRAM is so configured that operations, such as a refresh operation being unique to DRAM, are automatically performed by the inside thereof.
An example of the conventional non-synchronous semiconductor memory device configured to have a basic element of DRAM will hereinafter be described.
FIG. 1 shows an example of a configuration of the semiconductor memory device of this type. In this drawing, an address ADD is an external signal, and includes a row address designating a row of a memory cell array to be described below and a column address designating a column thereof.
An address input system 1 latches the address ADD and outputs an internal address LADD. An address transition detector circuit (ATD) 2 detects a transition of the internal address LADD and outputs a one-shot pulse signal OSP. An address multiplexer (MUX) 3 outputs, as an address MADD, one of the inputs which include an internal address LADD and a refresh address RADD to be described below.
A row decoder 6 decodes the address MADD for selecting a row of a memory cell array 7. The memory cell array 70 comprises a matrix array of memory cells similar to the general-purpose DRAM. A sense amplifier 71 amplifies a data signal on a bit line for a read operation. A column decoder 72 selects a column of the memory cell array 7. Although not illustrated herein, a precharge circuit for bit lines is provided accompanying the sense amplifier 71.
A refresh timer circuit 8G times a refresh time interval. A refresh control circuit 8H controls a series of refresh operations and generates a refresh control signal REFA for controlling a refresh timing accompanying to an external access and a refresh control signal REFB for controlling a self-refresh timing.
A refresh address generating circuit 8J generates an address RADD (hereinafter referred to as “refresh address”) to be used for a refresh operation. An internal pulse generating circuit 9 generates a row enable signal RE, a sense amplifier enable signal SE, a pre-charge enable signal PE and a column enable signal CE.
Other than the above-described circuits, there are further provided a system of circuits for controlling read and write operations, another system of circuits for generating a substrate potential of the memory cell array and still another system of circuits for read and write operations of data to the memory cell array.
The read and write operations and the refresh operation of the semiconductor memory device of the prior art shown in FIG. 1 will, in sequence, be described with reference to a timing chart of FIG. 2.
A. Read and Write Operations
A read operation according to an address access will be described as one example. In this case, a chip select signal ICS and an output enable signal /OE are low, while a write enable signal /WE is high, wherein the address ADD is an externally supplied signal.
The address ADD is an input to the address input system 1 and is latched as an output as the internal address LADD. Except for the refresh, this internal address LADD is supplied as the address MADD as an output of the multiplexer 3 to the row decoder 6. At a timing defined by the row enable signal RE, the row decoder 6 selects one word line in the memory cell array 7, so that data of memory cells connected to this single row of this word line are read out onto respective bit lines. These data signals are amplified by the sense amplifier 71 at a timing defined by the sense amplifier enable signal SE.
On the other hand, based on a column address (not illustrated) included in the address ADD, and at a timing defined by the column enable signal CE, the column decoder 72 selects a bit line of the memory cell array 7, so that data on this bit line is supplied as an external output signal through the data output circuit system (not illustrated). Prior to the operation of reading data from the memory cells, bit lines are pre-charged based on the pre-charge enable signal PE.
In the above-described series of read operations, a transition of the internal address LADD is detected by the address transition detector circuit 2 which outputs a one-shot pulse signal OSP. By triggering this one-shot pulse signal OSP, the internal pulse generating circuit 9 outputs, at appropriate timings, the above-described row enable signal RE, the sense amplifier enable signal SE, the pre-charge enable signal PE and the column enable signal CE.
Consequently, the data is read out of the memory cell designated by the address ADD and supplied to the outside.
B. Refresh Operation (in Read Mode)
A refresh operation in a read mode as one of the active modes will subsequently be described with reference to a timing chart shown in. FIG. 2(a).
In the read mode, the semiconductor memory device according to this conventional technique shows a sequential performance of both the refresh operation and the read operation in the same cycle in accordance with the specification.
The address input system 1 latches an external input address signal A0 as the address ADD and then outputs the internal address LADD. The address transition detector circuit 2 detects a transition of the internal address LADD and outputs the one-shot pulse signal OSP.
Upon receipt of the one-shot pulse signal OSP, the refresh control circuit 8H starts the refresh operation. Upon the start of the refresh operation, the refresh address generator circuit 8J generates and outputs a refresh row address RO as the refresh address RADD. Under the control of the refresh control circuit 8H, the address multiplexer 3 supplies the refresh address RADD (the refresh row address RO) as the address MADD to the row decoder 60.
On the other hand, the internal pulse generating circuit 9 receives an input of the refresh control signal REFB from the refresh control circuit 8H, and outputs the row enable signal RE and the sense amplifier enable signal SE. The row decoder 6 receives inputs of the address MADD and the row enable signal RE and selects a word line designated by the refresh address RO for a predetermined time period defined by the row enable signal RE. Data signals of the memory cells connected to the selected word line are amplified by the sense amplifiers and then re-stored therein, whereby the data of the memory cells for the single row designated by the refresh address RO have been refreshed.
After the refresh operation has been finished for the row designated by the refresh row address RO, then the read operation is made in the same cycle. For example, the address multiplexer 3 receives the internal address LADD from the address input system 1 and supplies the internal address LADD as the address MADD to the row decoder 6. The row decoder 6 selects the word line designated by the row address X0 entered as the input address MADD. The sense amplifier 71 amplifies the data signal appearing on the bit line in the memory cell array 7. The amplified data is provided as an external output through a data output circuit (not illustrated).
C. Refresh Operation (in Stand-by Mode)
A refresh operation in a stand-by mode will be described with reference to a timing chart shown in FIG. 2(b). In the stand-by mode, the refresh control circuit 8H measures an amount of time which has occurred from a time of the last external request for access, so that if the the amount of time exceeds a predetermined refresh time, then the refresh control circuit 8H outputs the refresh control signal REFB to start the self-refresh operation.
In the above-described active mode, after the refresh operation accompanying the read and write operation, the refresh control circuit 8H starts the timer. After the predetermined time has elapsed, the refresh is automatically started by triggering the timer. In either the stand-by mode or the active mode, the retention of the data is ensured without starting the refresh from the outside, similarly to the general-purpose SRAM.
Meanwhile, with the pseudo-SRAM in accordance with the above-conventional technique, it is necessary to pre-charge the bit line for a subsequent access until a predetermined time (hereinafter referred to as a recovery time TWR) from a time when the write enable signal is inactivated after the write operation to the memory cell has been made. Accordingly, it is difficult for the pseudo-SRAM that the recovery time TWR becomes zero. The pseudo-SRAM of this conventional technique maintains the write operation to the memory cell in a time period that the write enable signal is in the active state, for which reason in this time period, the refresh can be executed.
For the pseudo-SRAM, a write cycle time TWP has an upper limit of a write cycle time TWP for the refresh operation.
The pseudo-SRAM has strict limitations to the recovery time and the write cycle time, and is different in the specification from the general-purpose SRAM.
A data write method referred to herein as a “Late Write” has been presented for removing the limitations on the specification.
This late write will, hereinafter, be described briefly. In the memory cycle with an externally given request for the write access, a given write address and a given write data are taken into the semiconductor memory device, while those write address and write data as taken will be retained in the inside of the semiconductor memory device until the next request for write operation is entered. The write operation to the memory cell is not executed in this memory cycle, but will be executed in a future memory cycle of the entry of the next request for the write operation to the memory cell. The late write is that the write operation to the memory cell is delayed to the memory cycle of the entry of the next request for the write operation.
In accordance with the late write, it is unnecessary to write data into the memory cell within the memory cycle when these write data have been taken, for which reason it is unnecessary to pre-charge the bit line after the write operation, thereby allowing the recovery time TWR to be zero similarly to the general-purpose SRAM. In the later memory cycle that the data are written into the memory cell, the write address and the write data have already been taken, for which reason the activation of the write enable signal causes a prompt start the write operation to the memory cell. After the data write operation to the memory cell has been made, then it is unnecessary to maintain the word line to be selected even in the write cycle. This allows allocating a subsequent time period for the refresh. This further makes it unnecessary to limit the write cycle time for ensuring the refresh operation.
With the use of the late cycle, it is possible for the pseudo-SRAM to operate similarly to the general-purpose SRAM.
In accordance with the above-described late write, however, it is possible, in case, that a series of the refresh operation, the read operation and the write operation appears in a later memory cycle than the cycle of the actual write operation, thereby disturbing subsequent operation in the next memory cycle.
This problem will be described concretely with reference to FIG. 3. FIG. 3 shows a timing of writing data (not illustrated) to addresses A1.about.A3.
In the initial state, the write enable signal /WE is high, and the operation mode is the read mode. At a time t110, an address ADD is transitioned to an address A1. At a time t112, the write enable signal /WE transitions to low, whereby data externally designated in the current or present cycle is taken as well as previous data having already been taken in the previous cycle are stored in late-write to the memory cell.
At the time t110, the transition of the address ADD occurs, whereby the refresh is executed. At a time t111, the refresh is finished, whereby the read operation is started. Once the read operation has been started, it is prohibitive to interrupt the read operation in view of protecting the data. The above-described late write operation of the data will wait for the read operation to be completed. As a result, the late write, which should be executed in the write cycle to the address A1, is interrupted into the other write cycle to the next address A2, thereby disturbing the refresh in this next write cycle.
In accordance with this example, in the write cycle to the address A1, a series of the refresh operation, the read operation and the write operation is executed, thereby causing an increased consumption of current.
The present invention has been made in view of the above-circumstances. An object of the present invention is to provide a semiconductor memory device allowing the refresh operation to be free from any interruption by the late write and reducing a current consumption in a write cycle having the late write operation.